`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:10:16 06/03/2015
// Design Name:   MemoriaRegistros
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/TestMemReg.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MemoriaRegistros
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestMemReg;

	// Inputs
	reg [4:0] readPos1;
	reg [4:0] readPos2;
	reg [4:0] writePos;
	reg [31:0] writeData;
	reg clk;
	reg RegWrite;

	// Outputs
	wire [31:0] readData1;
	wire [31:0] readData2;

	// Instantiate the Unit Under Test (UUT)
	MemoriaRegistros uut (
		.readPos1(readPos1), 
		.readPos2(readPos2), 
		.writePos(writePos), 
		.writeData(writeData), 
		.readData1(readData1), 
		.readData2(readData2), 
		.clk(clk), 
		.RegWrite(RegWrite)
	);

	initial begin
		// Initialize Inputs
		readPos1 = 0;
		readPos2 = 0;
		writePos = 0;
		writeData = 0;
		clk = 0;
		RegWrite = 0;
		// Wait 100 ns for global reset to finish
		#100;   
		// Add stimulus here
		RegWrite = 1;  //escribimos un 0 en la pos 0
		#50;
		//AAAAAAAAA en la pos 1
		writePos = 1;
		writeData = 32'h AAAAAAAA;
		#10;
		//BBBBBBBB en la pos 2
		writePos = 2;
		writeData = 32'h BBBBBBBB;
		#10;
		//CCCCCCCC en la pos 3
		writePos = 3;
		writeData = 32'h CCCCCCCC;
		#10;
		//DDDDDDDD en la pos 4
		writePos = 4;
		writeData = 32'h DDDDDDDD;
		#10;
		//EEEEEEEE en la pos 5
		writePos = 5;
		writeData = 32'h EEEEEEEE;
		#10;
		//FFFFFFFF en la pos 6
		writePos = 6;
		writeData = 32'h FFFFFFFF;
		#10;
		//99999999 en la pos 6
		writePos = 7;
		writeData = 32'h 99999999;
		#10;
		RegWrite = 0;
		//Leemos todos
		readPos1 = 0;
		readPos2 = 1;
		#50;
		readPos1 = 2;
		readPos2 = 3;
		#50;
		readPos1 = 4;
		readPos2 = 5;
		#50;
		readPos1 = 6;
		readPos2 = 7;
		#50;
		
	end
	
	
always begin
 #1; clk = ~clk;
end
 
endmodule

